Abstract

   The hardware implementation of cryptographic algorithms is a timely method, providing efficient security solutions, both regarding the processing speed and the consumed power. The present-day FPGA platforms, which are the physical groundwork for such implementations, however they are not new engineering solutions, assert as the most efficient way to practically transpose the cryptographic algorithms, resulting optimized (concerning diversified aspects) cryptographic modules, respectively in the end, unmatched (concerning performance) ASIC chips. This paper presents a new hardware implementation for the enciphering block of the AES (Advanced Encryption Standard) symmetric cryptographic algorithm, using VHDL programming language and a hardware simulation of the resulted enciphering module.